`timescale 1ps / 1ps
module pc(input clk,
          input reset,
          input [31:0]npc,
          output reg [31:0]pc
        );
    
    initial begin
        pc = 0;
    end
    
    always @(posedge clk) begin
        pc = npc;
		  if(reset)
			pc = 0;
    end
    
endmodule // pc
